FIG. 1 is a sectional view of the conventional stacked cells, and the formation process is as described below. First, a field oxide layer 102 is selectively grown upon a p type silicon substrate 101, and then, a gate poly 103 and an oxide layer 104 are stacked. Then, a gate pattern is formed, and an n- region 105 is formed upon the silicon substrate 101. Then, side walls 106 are formed, and an n+ region 107 is formed, in such a manner that the portion connected to a node polysilicon 110 and the portion 113 connected to the bit line should become n+ regions. Thereafter, an HTO (high temperature oxide) 108 is formed, and a stack poly-silicon 109 is stacked upon the HTO 108. Then a buried contact is drilled by applying a photolithography process using a mask and then, a node polysilicon 110 is formed. Further, a capacitor insulating layer 111 is formed upon the node polysilicon 110, and a plate polysilicon 112 is stacked, thereby forming the capacitor section of the DRAM cell.
After forming the capacitor section, a contact portion 113 is formed for the contact of the bit lines. However, in the conventional DRAM cell manufactured through the process described above, the n+ region 107 which is connected to the node polysilicon 110 of the capacitor section gives an adverse influence to the leakage of current in the DRAM cell. Further, during the photolithography process for connecting the n+ region 107 to the node polysilicon 110 after stacking the stack polysilicon 109, there exists the risk that the node polysilicon 110 and the gate polysilicon 103 might be contacted to each other due to the misalingment. In order to reduce this risk, the gap between the gate polysilicon 103 and the node polysilicon 110 should be made large, and this brings the disadvantage that it increases the area of the DRAM cell.